This invention generally relates to electronic systems and in particular it relates to high speed voltage mode differential digital output drivers.
Output drivers used in high speed serial data communication systems must drive non-ideal channels that have a high load capacitance and attenuate high frequency information. A well designed driver must be capable of driving data with short rise and fall times under conditions of high load capacitance. In addition, it is beneficial for the driver to provide a method of pre-equalizing the transmit data to boost the high frequency content of the data to compensate for the channel attenuation.
Most prior art high-speed output data drivers implemented in CMOS use current-mode logic (CML) outputs or a source-follower output. CML, although using standard CMOS, has output rise and fall times set by the external or internal load resistance and capacitance since the CML driver is high impedance. CML outputs must also be terminated with a DC path to a power supply, which limits the range of output common-mode voltage and requires double terminating when AC-coupling is employed. CML output drivers are not suitable for very high data rate applications where load capacitance is significant because the resultant rise and fall times are significant when compared to a bit interval. A source-follower cannot provide the high signal swings since its maximum output is limited to the supply voltage minus the threshold voltage minus the saturation voltage of the source follower transistor. For high signal swings where large currents are required, the saturation voltage is significant and greatly reduces the maximum voltage drive. The threshold voltage also increases above its nominal value for a source follower because of the body effect. Source-followers also do not have symmetric rise and fall times and do not provide an easy technique for signal pre-equalization. Other high-speed prior art solutions are implemented using bipolar technologies such as a BiCMOS or SiGe process, or more exotic processes such as GaAs.
A differential driver consists of two feedback loops, and two inverter pairs. The two feedback loops regulate the source voltages for the two inverter pairs to two reference voltages. The two inverter pairs switch the output load RL and CL between the two regulated voltages in response to the input voltages. The reference voltages are created by a reference cell and set the output high and low voltages to be largely independent of process variations. Two additional circuits detect whenever a transition occurs in the output data. When there is a transition, a short duration pulse generates additional source and sink current at the outputs to reduce rise and fall times. A bit unit-interval pulse generator supplies extra current for an entire bit after a transition to pre-equalize the data prior to launch into a lossy medium.